Program Highlights

AI-Enabled VLSI Design Curriculum Integrating RTL-to-GDSII Workflow

Hands-On Training with 100 Hours of Cadence Industry Tool Access

Capstone Project Aligned to Industry-Grade Semiconductor Use Cases

Special Focus on Low-Power VLSI Design & Optimization Techniques

FPGA Prototyping on Cloud for Real-World Hardware Validation

About IIT Kharagpur

Established in 1951, IIT Kharagpur is India’s first Indian Institute of Technology and a pioneer of technical education, research, and innovation in the country. Over the decades, it has set the benchmark for engineering excellence, academic rigor, and industry relevance, shaping generations of leaders, technologists, and innovators.

IIT Kharagpur is globally recognized for its cutting-edge research, strong industry collaboration, and interdisciplinary approach to solving complex real-world problems. The institute consistently drives innovation across domains such as electronics, semiconductor technology, computer science, manufacturing, and applied sciences, contributing significantly to India’s technological and economic growth.

Program Directors

Prof. Mrigank Sharad

Assistant Professor (Grade-I), Rajendra Mishra School of Engineering Entrepreneurship Indian Institute of Technology Kharagpur

Nanoelectronics, VLSI Design, Digital and Mixed-Signal Systems, Semiconductor Device-Level to Circuit-Level Systems.

Prof. Amit Kumar Dutta

Associate Professor, G.S. Sanyal School of TelecommunicationIndian Institute of Technology Kharagpur

Physical Layer Communication Theory, Quantum Signal Processing, THz Communication, 6G Communications, VLSI Architecture for Communication Systems

Prof. Indrajit Chakrabarti

Professor, Department of Electronics & Electrical Communication EngineeringIndian Institute of Technology Kharagpur

VLSI Architectures for Image and Video Processing, Digital and Analog VLSI Design, Signal Processing Architectures for Communication Systems

The IIT Advantage

Experience Campus Immersion At IIT Kharagpur

Certification From IIT Kharagpur

Receive a Certificate of completion from IIT Kharagpur,
recognizing your achievement.

in Just 8 Months

How You Go From Learning to Orchestrating

Module 1: Verilog & Combinational RTL Foundations

Digital Design Foundations

Verilog Onboarding + First Verified Module

Combinational Modeling Styles + Decoder Design (QoR Awareness)

Module 2: Sequential RTL & FSM Controllers (Weeks 3-5)

Verilog System Design Essentials (Job-Aligned) + Code Experiments

Sequential RTL: DFFs & Counters (ASIC Flow Awareness)

FSM Controllers: Sequence, Vending Machine & Elevator Models

Vivado Flow Literacy

Module 3: Memory Blocks & Datapath Design

Memory in RTL: Register File, RAM & FIFO (FPGA + ASIC)

Datapath vs Control Logic

Fixed-Point Arithmetic, Truncation & Approximation Safety

Module 4: Low-Power RTL & AI-Augmented Power Aware Architecture

Design for power, not just functionality

Power Fundamentals I: 4 Power Types + Activity Tracing

Low-Power Techniques: 6 Key Levers

Power-Aware Architecture Design

Clock Gating Cell RTL (Production-Ready) + Verification

Module 5: FPGA Workflow & Cadence Synthesis Workflow / STA Literacy

Bridge FPGA and ASIC thinking

FPGA vs ASIC Synthesis Differences

Cadence Synthesis & STA: Genus + Tempus

TCL Scripting using AI Agents

Module 6: Capstone Kickoff

Capstone Kickoff: (Spec→Architecture) + (Algorithm→RTL Plan)

Controller FSM

Capstone Build II: Constraints, QoR Optimization for PPA

Module 7: Physical Design Foundations

Cadence P&R Baseline using Innovus

QoR Analysis & Iterative Improvements

Module 8: Floorplanning & Power Planning Foundations

Placement + Congestion Mitigation (Power tie-in)

CTS + Routing Overview (OSS) + Clock Power Intuition

Module 9: RTL → GDSII Deep Dive & Signoff

Cadence RTL → GDSII Baseline (Canonical Block)

Tool Awareness & Mapping to Open-Source Flows

Floorplanning & Locality (Power & Toggling Awareness)

Placement & Congestion Mitigation

CTS, Routing & Process / Corner Variations

Signoff Literacy: DRC, LVS & UPF Power Intent

Power Analysis & Multi-Knob Optimization (Voltus / Joules)

Module 10: AI-Driven Low Power Co-Optimization

ML-Based Architecture Design Space Exploration (DSE)

AI-Guided QoR Tuning Loop

Predictive STA & ECO Recommendations (Bounded)

Congestion & Floorplan Prediction

Module 11: Portfolio & Interview Readiness

Translate skills into job-ready outcomes

Portfolio Curation & Project Storytelling

Interview Readiness for RTL, PD & AI-EDA Roles

Module 12: Capstone Closure & Commercial Low-Power Methodology Showcase

Low-Power Methodology Showcase (Cadence-based) - demo + decision memo

Participants will gain hands-on experience with Industry-Grade Cadence Tools

AI Clinic

Through the Futurense AI Clinic, you’ll gain hands-on exposure to industry-grade semiconductor design workflows, from RTL development to physical implementation.

RTL to GDSII Implementation

Work through the complete VLSI design flow, design entry, simulation, synthesis, verification, and physical design.

Low-Power Design Engineering

Learn to architect and optimize power-efficient digital systems using industry-standard techniques and tools.

Cadence Tool Mastery

Gain practical experience on Cadence industry tools with 100 hours of dedicated access for real-time implementation and validation.

FPGA & AI-Enabled Workflow Exposure

Prototype designs on cloud-based FPGA platforms and explore AI-driven EDA workflows shaping next-generation chip design.

While mastering 20+ Tools

Digital Design & Simulation
RTL Verification
Logic Synthesis
Static Timing Analysis
FPGA Prototyping
Analog Simulation
RISC-V & Embedded Systems
IoT & System Integration
AI Hardware Design Workflow
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By The End, You’ll Be Able To Do All This

Design Complete RTL-to-GDSII Flows

Implement the full VLSI design cycle, RTL design, simulation, synthesis, physical design, timing analysis, and layout verification.

Architect Low-Power Digital Systems

Apply industry-standard low-power design techniques and optimize performance, area, and power (PPA) for scalable semiconductor systems.

Use Industry-Grade Cadence Tools

Execute professional EDA workflows using Cadence tools with practical exposure aligned to real semiconductor design environments.

Perform Static Timing & Physical Verification

Conduct timing analysis, placement, routing, clock-tree synthesis, DRC, and LVS checks using modern toolchains.

Prototype Designs on FPGA

Implement and validate digital designs on FPGA platforms for hardware-level testing and debugging

Use Modern Verification Frameworks

Create simulation environments and testbenches using Verilog, cocotb, and industry-style verification methodologies.

Understand AI-Driven EDA Workflows

Explore how AI techniques are integrated into modern semiconductor design automation pipelines.

This Program is for

Educational Qualification

- Bachelor’s degree (minimum 3 years) in ECE, EE, Electronics, CSE, Mechanical, Physics, or related disciplines.
- B.E. / B.Tech / M.Sc candidates are eligible.
- Minimum 60% marks or 6.0 CGPA (55% or 5.5 CGPA for candidates with 2+ years of work experience).

Work Experience

- Open to fresh graduates and working professionals.
- Suitable for early-career (1-3 years) and mid-career (3+ years) professionals aiming for VLSI, FPGA, ASIC, or semiconductor design roles.

Technical Readiness

- Basic understanding of digital electronics or programming fundamentals expected.
- Prior exposure to Verilog, RTL, FPGA, or embedded systems is an advantage, but not mandatory.

Learning Support

A pre-program Bridge Course ensures all learners are technically aligned and Day-1 ready, covering core electronics and VLSI fundamentals.

Educational Qualification

Short aptitude-based Qualifying Test (non-technical)

Qualifying Test

What You’ll Be Tested On

Analog Electronics

Digital Electronics

HDL/Verilog

Logical Reasoning

Duration: 90 minutes

Important Guidelines

Online, MCQ-based

Each section has a time limit and can be attempted only once

Do not refresh or close the browser during the qualifying test

Use latest versions of Chrome/Firefox on desktop/laptop

Keep pen and paper handy for rough work

You’ll receive qualifying test access only after completing registration

Electronics & ECE Graduates

Looking to move beyond theory and labs into production-grade RTL, ASIC physical design, and low-power silicon workflows used in real semiconductor teams.

Software / Embedded Engineers Transitioning to VLSI

Professionals aiming to shift from software or firmware roles into chip design, FPGA prototyping, or AI-enabled EDA workflows.

Early-Career VLSI & FPGA Engineers

Engineers who want signoff-grade exposure to Cadence tools, cloud FPGA, and RTL-to-GDSII flows to become industry-ready faster.

Mid-Career Professionals in Semiconductor Roles

Working professionals seeking to upskill in low-power design, physical design awareness, and AI-driven EDA orchestration for long-term growth in the VLSI ecosystem.

Roles That’ll Be Looking For You

RTL Design Engineer

₹6 – 18 LPA

lakhs per annum

VLSI Digital Design Engineer

₹6 – 22 LPA

lakhs per annum

ASIC Design Engineer (Frontend)

₹10 – 28 LPA

lakhs per annum

SoC Design Engineer (Digital Subsystems)

₹15 – 35 LPA

crores per annum

Micro-Architecture Engineer

₹14 – 32 LPA

crores per annum

Low-Power RTL Design Engineer

₹12 – 30 LPA

crores per annum

Physical Design Engineer (P&R)

₹8 – 25 LPA

lakhs per annum

Backend ASIC Engineer

₹9 – 28 LPA

lakhs per annum

Floorplanning Engineer

₹12 – 30 LPA

lakhs per annum

STA Engineer

₹8 – 24 LPA

crores per annum

CTS & Routing Engineer

₹10 – 26 LPA

crores per annum

Power Analysis & Optimization Engineer

₹12 – 35 LPA

crores per annum

Career Assistance

Young man studying math, writing notes with a pen while looking at a laptop screen displaying a right triangle and equations.

Profile, Narrative & Resume Building

Craft a recruiter-ready identity with optimized resumes, LinkedIn profiles, and a strong career narrative.

Students seated at desks with laptops attending an online video conference featuring a man speaking.

Career-Specific Training

Develop job-ready skills with role-focused training, capability tests, AI tools workshops, and continuous upskilling to match real hiring expectations.

Two men sitting at a table in an office, reviewing documents and discussing work with a laptop and coffee cups nearby.

Futurense Job Board - Exclusive Opportunities

Access curated, pre-vetted roles before they hit public portals, with priority visibility for Futurense learners.

Three young professionals enjoying coffee and snacks while collaborating around a laptop in a modern office.

Interview Playbooks & Cheat Sheets

Get insider interview guidance with structured playbooks: FAQs, sample answers, frameworks, recruiter insights, and round-wise preparation.

Two men reviewing a resume document together at a table in a modern office setting.

Mock Interviews with Experts

Experience real interview simulations with personalized feedback from mentors, industry leaders, and FLC members.

Mentor Referrals & Networking

Unlock referral advantages, insider recommendations, alumni-driven opportunities, and FLC mentorship that accelerates your career entry.

Two men sitting across a wooden table in an office, one taking notes and the other using a laptop.

Salary Negotiation Support

Get guidance on positioning, benchmarking, negotiation strategy, and communication to secure the compensation you deserve.

Our students are acing it!

They are working at companies which are a dream for most

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Fee Structure

Total Admission Fee

₹45,000

Apply Now
ComponentAmount (₹)
Program Fee₹45,000
GST (18%)As applicable
Registration Fee (Non-Refundable)*₹5,000 (Adjusted in Program Fee)
Total Payable₹45,000 + 18% GST

The registration fee of ₹5,000 is a one-time, non-refundable application processing fee, adjusted against the total program fee.

Payment of the registration fee is required at the time of application submission.

EMI options are available through partner NBFCs.

If a participant withdraws before the program start date, the program fee will be refunded, excluding:
Registration fee, GST, Any applicable subvention or processing charges.
No refunds are applicable once the program has commenced.

Optional 2-Day Campus Immersion at IIT Roorkee may be offered at an additional cost (subject to actuals).

Travel, boarding, and lodging expenses for campus immersion (if opted) will be borne by the participant.

Application Deadline

Dummy Date Text

Admissions close once the required number of students is enrolled for the upcoming cohort. Apply early to secure your seat.

How it Works

Application Process

1

Submit Your Application

Apply online with your basic details and pay the ₹5,000 non-refundable registration fee to complete your application.

2

Pre-Screening Assessment

Take a pre-screening test to assess your technical readiness and suitability for the Forward Deployed Engineer role.

3

Offer & Begin Your Learning Journey

Receive your offer letter, complete the fee payment, and get immediate access to the Futurense Bridge Course before classes begin.

Traditional VLSI Programs vs. IIT Kharagpur’s AI-Enabled VLSI Design

Dimension

This Programme

Other Programme

Core Philosophy
Production-grade RTL-to-GDSII engineering, focused on low-power, AI-assisted silicon design and real sign-off constraints
Tool-centric or theory-heavy learning with limited exposure to real silicon constraints
Role Orientation
Industry-aligned roles across RTL Design, Physical Design, FPGA, Low-Power & AI-EDA workflows
Academic or entry-level focus without clear mapping to production VLSI roles
Curriculum Design
End-to-end flow: RTL → Synthesis → STA → Physical Design → Sign-off, integrated with AI-EDA
Fragmented modules taught in isolation (RTL, PD, or verification separately)
Learning Style
Evidence-first, hands-on labs, cloud FPGA prototyping, Cadence sign-off flows, and system-level capstones
Lecture-driven learning with simulations and small academic assignments
Production Readiness
Emphasis on PPA trade-offs, timing closure, power intent (UPF), congestion, and sign-off literacy
Limited focus on production realities like timing, power leakage, or closure loops
EDA & Tool Exposure
Industry-standard Cadence tools, cloud FPGA workflows, and AI-guided design space exploration
Local tools, open-source only, or limited exposure to professional EDA environments
AI Integration
AI-assisted EDA workflows for DSE, QoR tuning, and agentic orchestration (Cerebrus-style)
Little to no exposure to AI-enabled design or automation in VLSI
Portfolio Output
Sign-off-ready evidence packs: waveforms, QoR reports, logs, and RTL-to-GDSII capstone
Academic projects or RTL demos without production-grade artefacts

Feeling Underconfident About Your Skills?

Kick things off with a 2-Week Bridge Course that gets you course-ready

Young man in a blue shirt resting his chin on his hand, looking thoughtfully upward.

What you'll learn:

Semiconductor Fundamentals

Digital Electronics

Analog Electronics

Fundamentals of HDL

Worth ₹29,000

Included free with your enrollment.

Led by the Futurense Leadership Council (FLC)

 A collective of CXOs, AI leaders, and digital transformation heads from
Fortune 500 companies shaping the AI-native workforce.

A V Rahul

Director, Analytics, - Barracuda

Aditya Khandekar

President, Corridor Platforms

Akshay Kumar

Research & Analytics Leader

Alok Tiwari

Director of Analytics, Junglee Games

Anand Das

Chief Digital & AI Officer, TVS Motors

Aneel kumar

Global Chapter Leader - ICSS, DD&T

Anirban Nandi

Head of AI Products & Analytics (Vice President), Rakuten India

Ankit Mogra

Director – Insights & Analytics, Ather Energy

Anupam Gupta

Independent Consultant – AI/ML Product Development, Amplify Health

Arpit Agarwal

Data Science Manager, Google

Arvind Balasundram

Executive Director, Commercial Insights & Analytics

Ashish Dabas

Vice President, Capital One

Bhairav M

Senior Manager Data Science and Product Management

Bhargab Dutta

Chief Digital Officer, Centuryply

Deepa Mahesh

Head of Strategy & Operations, Board Member

Divesh Singla

SVP, Global Operations Services and Managing Director, India & Philippines, SignantHealth

Indrani Goswami

Director of Analytics, NYKAA

Ishu Jain

Head of Analytics

Kaushik Das

Managing Director, JCPenney

Krithika Muthukrishnan

Chief Data Science Officer, Scripbox

Madhu Hosadurga

Global Vice President, Enterprise AI, Schneider Electric

Madhurima Agarwal

Managing Director - Microsoft for Startups

Monica S Pirgal

Chief Executive Officer, Bhartiya Converge

Muthumari S

Global Head of Data & AI Studio

Nithya Subramanian

Senior Director Data & AI COE - Best Buy

Nitin Srivastava

Global Head of Data and Analytics, Dr. Martens plc

Pankaj Rai 

Group Chief Data and Analytics Officer, Aditya Birla Group

Pankaj Srivastava

Partner, PwC

Praveen Sathyadev

Head - EU/UK Business Growth (VP) - Analytics, Insights and AI, Course5i

Ruchika Singh

Director, Data Science & Insights, Spotify

Satyakam Mohanty

Founder & Managing Partner, Wyser

Saurabh Agarwal

Chief Executive Officer

Saurabh Kumar

Director - Data Engineering

Sharmistha Chaterjee

Executive Engineering Manager - Head of Software and Systems Engineering, Commonwealth Bank

Shirsha Ray Chaudhuri

Director of Engineering

Srini Oduru

Head of IT Delivery and Operations, Cervello India

Sulabh Jain

Chief Analytics Officer

Sumon Mal

Head of Backend Engineering, Sony LIV

Supria Dhanda

Co-Founder & Managing Partner, Wyser

Swati Jain

Partner - Digital, AI & Analytics, Deloitte

Tushar Chahal

Chief Technology Officer, Numisma Bank

Tushar Sahu

Director Engineering, Google

Vidhi Chugh

AI Executive | Microsoft MVP

Vishal Nagpal

Director of Data and AI at Best Buy

Vishal Nagpal

Director of Data and AI at Best Buy

Vidhi Chugh

AI Executive | Microsoft MVP

Tushar Sahu

Director Engineering, Google

Tushar Chahal

Chief Technology Officer, Numisma Bank

Swati Jain

Partner - Digital, AI & Analytics, Deloitte

Supria Dhanda

Co-Founder & Managing Partner, Wyser

Sumon Mal

Head of Backend Engineering, Sony LIV

Sulabh Jain

Chief Analytics Officer

Srini Oduru

Head of IT Delivery and Operations, Cervello India

Shirsha Ray Chaudhuri

Director of Engineering

Sharmistha Chaterjee

Executive Engineering Manager - Head of Software and Systems Engineering, Commonwealth Bank

Saurabh Kumar

Director - Data Engineering

Saurabh Agarwal

Chief Executive Officer

Satyakam Mohanty

Founder & Managing Partner, Wyser

Ruchika Singh

Director, Data Science & Insights, Spotify

Praveen Sathyadev

Head - EU/UK Business Growth (VP) - Analytics, Insights and AI, Course5i

Pankaj Srivastava

Partner, PwC

Pankaj Rai 

Group Chief Data and Analytics Officer, Aditya Birla Group

Nitin Srivastava

Global Head of Data and Analytics, Dr. Martens plc

Nithya Subramanian

Senior Director Data & AI COE - Best Buy

Muthumari S

Global Head of Data & AI Studio

Monica S Pirgal

Chief Executive Officer, Bhartiya Converge

Madhurima Agarwal

Managing Director - Microsoft for Startups

Madhu Hosadurga

Global Vice President, Enterprise AI, Schneider Electric

Krithika Muthukrishnan

Chief Data Science Officer, Scripbox

Kaushik Das

Managing Director, JCPenney

Ishu Jain

Head of Analytics

Indrani Goswami

Director of Analytics, NYKAA

Divesh Singla

SVP, Global Operations Services and Managing Director, India & Philippines, SignantHealth

Deepa Mahesh

Head of Strategy & Operations, Board Member

Bhargab Dutta

Chief Digital Officer, Centuryply

Bhairav M

Senior Manager Data Science and Product Management

Ashish Dabas

Vice President, Capital One

Arvind Balasundram

Executive Director, Commercial Insights & Analytics

Arpit Agarwal

Data Science Manager, Google

Anupam Gupta

Independent Consultant – AI/ML Product Development, Amplify Health

Ankit Mogra

Director – Insights & Analytics, Ather Energy

Anirban Nandi

Head of AI Products & Analytics (Vice President), Rakuten India

Aneel kumar

Global Chapter Leader - ICSS, DD&T

Anand Das

Chief Digital & AI Officer, TVS Motors

Alok Tiwari

Director of Analytics, Junglee Games

Akshay Kumar

Research & Analytics Leader

Aditya Khandekar

President, Corridor Platforms

A V Rahul

Director, Analytics, - Barracuda

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Ready to Design the Next Generation of AI-Optimized Silicon?

Low-power design, cloud FPGA, and AI-driven EDA are redefining how chips are built. Engineers trained for yesterday won’t make tomorrow’s silicon.

Frequently Asked Questions

We know you might have some questions before getting started in our platform

Program Overview
Curriculum and Learning
Career Outcomes

What is the name of the certificate program that IIT offers?

The program is called Executive Post Graduate Certification in AI-Enabled VLSI Design, and it is offered by the Indian Institute of Technology Kharagpur (IIT Kharagpur).

What is the duration of the program, and when does the first cohort begin?

The program duration is  8 months. The cohort will start from April 2026 (Tentative).

What are the eligibility criteria for this program, and who should ideally enroll?

Qualification:

B.Tech / M.Tech, B.E / M.E (4th Year Students or Completed)
(Electronics, ECE, EE, VLSI, Electrical, Instrumentation, CS, IT)

M.Sc (Electronics / Physics / Semiconductor Technology) or MCA
Experience
Currently in 4th Year/ Graduated Fresher/Working professional.

Candidates from other engineering disciplines with demonstrable exposure to embedded systems, Digital Electronics, HDL, or Semiconductor fundamentals may be considered on a case-by-case basis.

Minimum Academic Requirement:

50% aggregate (or equivalent CGPA) from a recognised university

How can I apply to the Executive Post Graduate Certification in AI-Enabled VLSI Design?

Fill the Apply Now form and click submit.

When will the application process for the program start?

The application process has already begun - Apply Now Link.

What is the program fee, and what financing options are available?

The program fees - Rs 1,25,000 + 18% GST
Financing options are available; kindly check with your counselors for more information.

How is the teaching format structured for this program?

The program is delivered through 100% live online classes delivered by IIT Kharagpur faculty and industry experts.

Why is this program considered unique compared to other certifications in VLSI?

The program offers a unique blend of three main pillars
- The Precision of Cadence: Master industry-standard ASIC implementation from Genus synthesis to Tempus signoff
- The Reality of Xilinx Vivado: FPGA workflow experience for hardware-proven rapid prototyping
-The Industry standard flow: The program covers the complete RTL to GDSII flow with AI-driven PPA optimization reports, reworking, and mission-critical low-power design techniques.

Will there be any additional cost for attending the optional 3-day IIT Kharagpur campus immersion?

Yes, around Rs 10,000 will be required to be paid to the institute at the time of the immersion. The details regarding the same will be provided near the immersion dates.

Will hostel accommodation be provided for outstation candidates from different states during immersion?

Yes, accommodation booking will be enabled for such candidates (subject to availability).

Is there a selection process?

Yes. The admission process involves five steps:
1. Submit Application: Share your academic and professional background
2. Profile Review: Shortlisting by the technical committee
3. Prescreening Test: A test to evaluate your knowledge of the subject
3. Offer Letter: Receive your invitation to join the cohort
4. Block Your Seat: Secure your spot in the upcoming batch

What are the documents to be submitted for the application?

The following are the documents required:
-Aadhar Card
-DOB (in correct format and as per Aadhar Card - DD/MM/YYYY)
-Resume
-Graduation Marksheet and Degree (cross-verified with scores entered in the application portal)
-12th Marks (cross-verified)
-Previous Experience Letter, Offer Letter, and Salary Slip

Will there be any pre-screen exams for enrolling in the Program?

Yes, there will be a pre-screening exam. A basic understanding of Digital Electronics, Analog Electronics, Logical Reasoning, and Verilog coding skills would help qualify for the pre-screening test

Should I have experience in coding to qualify for the pre-screening exam?

Basic Verilog coding skills would help qualify for the pre-screening test, as well as provide a smooth start for the certification.

What is the Payment Schedule and Process?

Full fee payment of ₹1,25,000 + GST must be completed within 5 days of receiving the offer letter.
A non-refundable application deposit of ₹5,000 is required at the time of application submission (adjusted in the final fee)
Loan options are also available.

Can I self-fund this program?

Yes. If you or your family are funding the program, you can choose to self-fund either partially or in full.

Does Futurense help with loans?

Yes. Futurense has partnered with various financial institutions to offer financial assistance.

What is the interest rate on the loans?

Interest rates vary depending on the repayment plan and financial partner. Rates are described as reasonable and competitive considering the recent rise in unsecured loan rates in India.

What are the documents I should keep handy?

PAN
Aadhar
Last 3 months’ bank statements

What areas of VLSI design does this program cover?

The program provides comprehensive coverage across the following areas:
- Foundations for digital design & High-Fidelity RTL: Verilog, low-power fundamentals, FSM controllers, memory inference
- FPGA mapped workflow: Using VIVADO IDE and Verilog coding, FPGA workflows can be targeted
- ASIC Implementation & Signoff: Netlist-to-GDSII path, floorplanning, CTS, DRC/LVS, STA, power analysis
- AI-Integrated EDA & Agentic Loops: AI constraint tuning of reports for better design

What tools and platforms are covered in this program?

The program provides hands-on experience with industry-leading tools:
- Vivado IDE
- Cadence Tools: Xcelium, Genus, Innovus, Tempus, Voltus
- Programming & Automation: Verilog, Tcl Scripting basics.

What makes the AI integration in this program unique?

Unlike traditional VLSI courses that rely on manual iteration, this program integrates AI-driven workflows:
- ML-based Design Space Exploration (DSE) to optimize Power, Performance, and Area (PPA) reports.
- Predictive Static Timing Analysis (STA)

What makes this certificate program particularly suitable for engineers and tech professionals?

The program provides full-stack ownership from RTL to GDSII, hands-on experience with commercial-grade toolchains used in the semiconductor industry. AI-driven automation capabilities that represent the future of chip design. This comprehensive approach makes graduates ready for future senior technical roles in the semiconductor industry.

How does the program enable participants to specialize in their specific engineering domains?

The program provides modular training and industry-standard toolkits that can be adapted for different application domains in semiconductor design. Participants work on real-world capstone projects that can be tailored to their areas of interest.

What are some practical projects or hands-on learning outcomes included in the course?

The program includes the following sample capstone projects:
1-Hardware-Accelerated Audio Signal Processing with Neural Network Classifier
2-Tiny YOLO-Based Object Detection Accelerator for Edge AI
3-Accelerator for Optical Flow Estimation and Object Detection for Automated Vehicles

Who is the program director, and why is their expertise significant?

Prof. Mrigank Sharad, his expertise in fields of Nanoelectronics, VLSI Design, Digital and Mixed-Signal Systems is very critical in modern-day electronics. These expertise are foundational to the next generation of energy-efficient AI hardware and high-performance communication systems.

What makes IIT Kharagpur a trendsetter in technological education, particularly in VLSI?

IIT Kharagpur holds distinguished credentials of being India’s First IIT, established in 1951 as an Institute of National Importance. IIT Kharagpur remains a trendsetter by combining India’s one of the most advanced VLSI research infrastructure with a specialized 'RTL-to-Silicon' curriculum that bridges the gap between fundamental  and industry-scale chip architecture."

How do industry leaders contribute to the program?

The program merges IIT Kharagpur’s academic rigor with industry’s most advanced practices. The curriculum is designed to ensure graduates are prepared for the shift toward AI-integrated design and industry-standard tool flow that the semiconductor industry prefers.

What job roles can participants expect to pursue after completing this program?

Graduates will be positioned for the following roles:
- RTL Design Engineer
- FPGA Design Engineer / Architect
- ASIC Implementation Engineer
- Physical Design Engineer
- Low Power Design Specialist
- AI-EDA Integration Specialist

How does having skills in AI-integrated EDA impact salary and job prospects?

These are cutting-edge, high-demand skills in the semiconductor industry. As companies increasingly adopt AI-driven design automation, professionals with expertise in these areas command premium compensation and have access to specialized roles that are emerging in the industry.

Why will this certificate program future-proof careers in a rapidly evolving market?

The program equips learners with the complete stack, from RTL fundamentals to AI-driven automation. By mastering both traditional VLSI methodologies and emerging technologies, graduates are prepared not just for current roles but for the future direction of the semiconductor industry.

What certification will I receive upon completion?

Upon successful completion of the program, candidates receive an Executive Post Graduate Certification in AI-Enabled VLSI Design from IIT Kharagpur.

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