Days
Hours
Minutes
Sec
Architect the Silicon of Tomorrow: From Low-Power RTL to AI-Optimized GDSII.


Established in 1951, IIT Kharagpur is India’s first Indian Institute of Technology and a pioneer of technical education, research, and innovation in the country. Over the decades, it has set the benchmark for engineering excellence, academic rigor, and industry relevance, shaping generations of leaders, technologists, and innovators.
IIT Kharagpur is globally recognized for its cutting-edge research, strong industry collaboration, and interdisciplinary approach to solving complex real-world problems. The institute consistently drives innovation across domains such as electronics, semiconductor technology, computer science, manufacturing, and applied sciences, contributing significantly to India’s technological and economic growth.



Receive a Certificate of completion from IIT Kharagpur,
recognizing your achievement.
in Just 8 Months
Module 1: Verilog & Combinational RTL Foundations
Module 2: Sequential RTL & FSM Controllers (Weeks 3-5)
Module 3: Memory Blocks & Datapath Design
Module 4: Low-Power RTL & AI-Augmented Power Aware Architecture
Module 5: FPGA Workflow & Cadence Synthesis Workflow / STA Literacy
Module 6: Capstone Kickoff
Module 7: Physical Design Foundations
Module 8: Floorplanning & Power Planning Foundations
Module 9: RTL → GDSII Deep Dive & Signoff
Module 10: AI-Driven Low Power Co-Optimization
Module 11: Portfolio & Interview Readiness
Module 12: Capstone Closure & Commercial Low-Power Methodology Showcase

Through the Futurense AI Clinic, you’ll gain hands-on exposure to industry-grade semiconductor design workflows, from RTL development to physical implementation.
Work through the complete VLSI design flow, design entry, simulation, synthesis, verification, and physical design.
Learn to architect and optimize power-efficient digital systems using industry-standard techniques and tools.
Gain practical experience on Cadence industry tools with 100 hours of dedicated access for real-time implementation and validation.
Prototype designs on cloud-based FPGA platforms and explore AI-driven EDA workflows shaping next-generation chip design.









- Bachelor’s degree (minimum 3 years) in ECE, EE, Electronics, CSE, Mechanical, Physics, or related disciplines.
- B.E. / B.Tech / M.Sc candidates are eligible.
- Minimum 60% marks or 6.0 CGPA (55% or 5.5 CGPA for candidates with 2+ years of work experience).
- Open to fresh graduates and working professionals.
- Suitable for early-career (1-3 years) and mid-career (3+ years) professionals aiming for VLSI, FPGA, ASIC, or semiconductor design roles.
- Basic understanding of digital electronics or programming fundamentals expected.
- Prior exposure to Verilog, RTL, FPGA, or embedded systems is an advantage, but not mandatory.
A pre-program Bridge Course ensures all learners are technically aligned and Day-1 ready, covering core electronics and VLSI fundamentals.
Short aptitude-based Qualifying Test (non-technical)
What You’ll Be Tested On
Duration: 90 minutes
Looking to move beyond theory and labs into production-grade RTL, ASIC physical design, and low-power silicon workflows used in real semiconductor teams.
Professionals aiming to shift from software or firmware roles into chip design, FPGA prototyping, or AI-enabled EDA workflows.
Engineers who want signoff-grade exposure to Cadence tools, cloud FPGA, and RTL-to-GDSII flows to become industry-ready faster.
Working professionals seeking to upskill in low-power design, physical design awareness, and AI-driven EDA orchestration for long-term growth in the VLSI ecosystem.
They are working at companies which are a dream for most




Subtext
| Component | Amount (₹) |
|---|---|
| Program Fee | ₹45,000 |
| GST (18%) | As applicable |
| Registration Fee (Non-Refundable)* | ₹5,000 (Adjusted in Program Fee) |
| Total Payable | ₹45,000 + 18% GST |
Admissions close once the required number of students is enrolled for the upcoming cohort. Apply early to secure your seat.
How it Works
Apply online with your basic details and pay the ₹5,000 non-refundable registration fee to complete your application.
Take a pre-screening test to assess your technical readiness and suitability for the Forward Deployed Engineer role.
Receive your offer letter, complete the fee payment, and get immediate access to the Futurense Bridge Course before classes begin.
Kick things off with a 2-Week Bridge Course that gets you course-ready

Worth ₹29,000
A collective of CXOs, AI leaders, and digital transformation heads from
Fortune 500 companies shaping the AI-native workforce.

























































































Low-power design, cloud FPGA, and AI-driven EDA are redefining how chips are built. Engineers trained for yesterday won’t make tomorrow’s silicon.
We know you might have some questions before getting started in our platform
The program is called Executive Post Graduate Certification in AI-Enabled VLSI Design, and it is offered by the Indian Institute of Technology Kharagpur (IIT Kharagpur).
The program duration is 8 months. The cohort will start from April 2026 (Tentative).
Qualification:
B.Tech / M.Tech, B.E / M.E (4th Year Students or Completed)
(Electronics, ECE, EE, VLSI, Electrical, Instrumentation, CS, IT)
M.Sc (Electronics / Physics / Semiconductor Technology) or MCA
Experience
Currently in 4th Year/ Graduated Fresher/Working professional.
Candidates from other engineering disciplines with demonstrable exposure to embedded systems, Digital Electronics, HDL, or Semiconductor fundamentals may be considered on a case-by-case basis.
Minimum Academic Requirement:
50% aggregate (or equivalent CGPA) from a recognised university
Fill the Apply Now form and click submit.
The application process has already begun - Apply Now Link.
The program fees - Rs 1,25,000 + 18% GST
Financing options are available; kindly check with your counselors for more information.
The program is delivered through 100% live online classes delivered by IIT Kharagpur faculty and industry experts.
The program offers a unique blend of three main pillars
- The Precision of Cadence: Master industry-standard ASIC implementation from Genus synthesis to Tempus signoff
- The Reality of Xilinx Vivado: FPGA workflow experience for hardware-proven rapid prototyping
-The Industry standard flow: The program covers the complete RTL to GDSII flow with AI-driven PPA optimization reports, reworking, and mission-critical low-power design techniques.
Yes, around Rs 10,000 will be required to be paid to the institute at the time of the immersion. The details regarding the same will be provided near the immersion dates.
Yes, accommodation booking will be enabled for such candidates (subject to availability).
Yes. The admission process involves five steps:
1. Submit Application: Share your academic and professional background
2. Profile Review: Shortlisting by the technical committee
3. Prescreening Test: A test to evaluate your knowledge of the subject
3. Offer Letter: Receive your invitation to join the cohort
4. Block Your Seat: Secure your spot in the upcoming batch
The following are the documents required:
-Aadhar Card
-DOB (in correct format and as per Aadhar Card - DD/MM/YYYY)
-Resume
-Graduation Marksheet and Degree (cross-verified with scores entered in the application portal)
-12th Marks (cross-verified)
-Previous Experience Letter, Offer Letter, and Salary Slip
Yes, there will be a pre-screening exam. A basic understanding of Digital Electronics, Analog Electronics, Logical Reasoning, and Verilog coding skills would help qualify for the pre-screening test
Basic Verilog coding skills would help qualify for the pre-screening test, as well as provide a smooth start for the certification.
Full fee payment of ₹1,25,000 + GST must be completed within 5 days of receiving the offer letter.
A non-refundable application deposit of ₹5,000 is required at the time of application submission (adjusted in the final fee)
Loan options are also available.
Yes. If you or your family are funding the program, you can choose to self-fund either partially or in full.
Yes. Futurense has partnered with various financial institutions to offer financial assistance.
Interest rates vary depending on the repayment plan and financial partner. Rates are described as reasonable and competitive considering the recent rise in unsecured loan rates in India.
PAN
Aadhar
Last 3 months’ bank statements
The program provides comprehensive coverage across the following areas:
- Foundations for digital design & High-Fidelity RTL: Verilog, low-power fundamentals, FSM controllers, memory inference
- FPGA mapped workflow: Using VIVADO IDE and Verilog coding, FPGA workflows can be targeted
- ASIC Implementation & Signoff: Netlist-to-GDSII path, floorplanning, CTS, DRC/LVS, STA, power analysis
- AI-Integrated EDA & Agentic Loops: AI constraint tuning of reports for better design
The program provides hands-on experience with industry-leading tools:
- Vivado IDE
- Cadence Tools: Xcelium, Genus, Innovus, Tempus, Voltus
- Programming & Automation: Verilog, Tcl Scripting basics.
Unlike traditional VLSI courses that rely on manual iteration, this program integrates AI-driven workflows:
- ML-based Design Space Exploration (DSE) to optimize Power, Performance, and Area (PPA) reports.
- Predictive Static Timing Analysis (STA)
The program provides full-stack ownership from RTL to GDSII, hands-on experience with commercial-grade toolchains used in the semiconductor industry. AI-driven automation capabilities that represent the future of chip design. This comprehensive approach makes graduates ready for future senior technical roles in the semiconductor industry.
The program provides modular training and industry-standard toolkits that can be adapted for different application domains in semiconductor design. Participants work on real-world capstone projects that can be tailored to their areas of interest.
The program includes the following sample capstone projects:
1-Hardware-Accelerated Audio Signal Processing with Neural Network Classifier
2-Tiny YOLO-Based Object Detection Accelerator for Edge AI
3-Accelerator for Optical Flow Estimation and Object Detection for Automated Vehicles
Prof. Mrigank Sharad, his expertise in fields of Nanoelectronics, VLSI Design, Digital and Mixed-Signal Systems is very critical in modern-day electronics. These expertise are foundational to the next generation of energy-efficient AI hardware and high-performance communication systems.
IIT Kharagpur holds distinguished credentials of being India’s First IIT, established in 1951 as an Institute of National Importance. IIT Kharagpur remains a trendsetter by combining India’s one of the most advanced VLSI research infrastructure with a specialized 'RTL-to-Silicon' curriculum that bridges the gap between fundamental and industry-scale chip architecture."
The program merges IIT Kharagpur’s academic rigor with industry’s most advanced practices. The curriculum is designed to ensure graduates are prepared for the shift toward AI-integrated design and industry-standard tool flow that the semiconductor industry prefers.
Graduates will be positioned for the following roles:
- RTL Design Engineer
- FPGA Design Engineer / Architect
- ASIC Implementation Engineer
- Physical Design Engineer
- Low Power Design Specialist
- AI-EDA Integration Specialist
These are cutting-edge, high-demand skills in the semiconductor industry. As companies increasingly adopt AI-driven design automation, professionals with expertise in these areas command premium compensation and have access to specialized roles that are emerging in the industry.
The program equips learners with the complete stack, from RTL fundamentals to AI-driven automation. By mastering both traditional VLSI methodologies and emerging technologies, graduates are prepared not just for current roles but for the future direction of the semiconductor industry.
Upon successful completion of the program, candidates receive an Executive Post Graduate Certification in AI-Enabled VLSI Design from IIT Kharagpur.